Design & Reuse
arrow AMBA AHB / APB/ AXI (192)
arrow CXL (18)
arrow D2D (58)
arrow Gen-Z (6)
arrow HDMI (83)
arrow I2C (98)
arrow Interlaken (2)
arrow MIL-STD-1553 (3)
arrow MIPI (460)
arrow Multi-Protocol PHY (37)
arrow PCI (254)
arrow RapidIO (6)
arrow SAS (6)
arrow SATA (95)
arrow Smart Card (6)
arrow USB (390)
arrow V-by-One (22)
arrow VESA (73)
arrow Other (66)
192 IP
101
0.118
AXI system Peripheral IP, AXI Bus System Interconnect, Soft IP
AXI bus interconnect....
102
0.118
AXI system Peripheral IP, AXI to AXI Bridge, Soft IP
AMBA AXI to AXI Bridge....
103
0.118
AXI system Peripheral IP, AXI/APB host bridge, Soft IP
AXI/APB host bridge controller....
104
0.118
AXI system Peripheral IP, Cache Controller, L2 Cache, Soft IP
L2 cache controller with AXI interface....
105
0.118
AXI system Peripheral IP, DMA controller for AXI master port and slave port (32 - bit, 64 - bit and 128 - bit), 8 channels DMA, Soft IP
DMA controller with AXI interface....
106
0.118
AXI system Peripheral IP, Interrupt Controller, Soft IP
Generic Interrupt Controller with AXI interface. Faraday's FTINTC030 Generic interrupt controller supports software generated interrupt, private perip...
107
0.0
I2C/SMBus Master/Slave Controller w/FIFO (AXI/AHB/APB)
The Digital Blocks DB-I2C-SMBus-MS-AMBA Controller IP Core is an I2C/SMBus Master/Slave Controller, interfacing a microprocessor via the AMBA AXI, AHB...
108
0.0
I3C Master / Slave Controller w/FIFO (APB Bus)
The Digital Blocks DB-I3C-MS-APB Controller IP Core interfaces a microprocessor via the AMBA APB Bus to an I3C Bus, compliant to the MIPI I3C – Improv...
109
0.0
I3C Master Controller w/FIFO (APB Bus)
The Digital Blocks DB-I3C-MS-APB Controller IP Core interfaces a microprocessor via the AMBA APB Bus to an I3C Bus, compliant to the MIPI I3C – Improv...
110
0.0
I3C Slave Controller w/FIFO (APB Bus)
The Digital Blocks DB-I3C-S-APB Controller IP Core interfaces a microprocessor via the AMBA APB Bus to an I3C Bus, compliant to the MIPI I3C – Improve...
111
0.0
Scatter-Gather DMA - AXI4-Stream to/from AXI4 Memory Map Transfers
The Digital Blocks DB-DMAC-MC-AXI4-MM-STREAM Verilog RTL IP Core is a Multi-Channel Scatter-Gather DMA Controller that transfers data between AXI4 Mem...
112
0.0
PCIe 1.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with Built-in DMA and Configurable AMBA AXI Interconnect
Rambus PCIe 1.1 Controller with AXI is a configurable and scalable PCIe controller Soft IP designed for ASIC and FPGA implementation. Rambus PCIe 1.1 ...
113
0.0
PCIe 2.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with Built-in DMA and Configurable AMBA AXI Interconnect
Rambus PCIe 2.1 Controller with AXI is a configurable and scalable PCIe controller Soft IP designed for ASIC and FPGA implementation. Rambus PCIe 2.1 ...
114
0.0
PCIe 3.0, 2.1, 1.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with AMBA AXI User Interface
Rambus PCIe 3.0 with AXI is a configurable and scalable PCIe controller Soft IP designed for ASIC and FPGA implementation. Rambus PCIe 3.0 with AXI is...
115
0.0
PCIe 4.0 Controller with AMBA AXI interface
Rambus PCIe 4.0 Controller is a configurable and scalable PCIe controller Soft IP designed for ASIC and FPGA implementation. The Rambus PCIe 4.0 Contr...
116
0.0
PCIe 5.0 Controller with AMBA AXI interface
Rambus PCIe 5.0 Controller is a configurable and scalable PCIe controller Soft IP designed for ASIC and FPGA implementation. Rambus PCIe 5.0 Controlle...
117
0.0
UDP/IP Hardware Protocol Stack - 100G
The Digital Blocks DB-UDP-IP-100GbE-AMBA is a UDP/IP Hardware Stack / UDP Off-load Engine (UOE) with low latency, high-performance targeting 100 GbE n...
118
0.0
UDP/IP Hardware Protocol Stack - 10G
The Digital Blocks DB-UDP-IP-10GbE-AMBA is a UDP/IP Hardware Stack / UDP Off-load Engine (UOE) with low latency, high-performance targeting 10 GbE net...
119
0.0
UDP/IP Hardware Protocol Stack - 1G
The Digital Blocks DB-UDP-IP-1GbE-AMBA is a UDP/IP Hardware Stack / UDP Off-load Engine (UOE) with low latency, high-performance targeting 10 GbE netw...
120
0.0
UDP/IP Hardware Protocol Stack - 25G
The Digital Blocks DB-UDP-IP-25GbE-AMBA is a UDP/IP Hardware Stack / UDP Off-load Engine (UOE) with low latency, high-performance targeting 25 GbE net...
121
0.0
UDP/IP Hardware Protocol Stack - 40G
The Digital Blocks DB-UDP-IP-40GbE-AMBA is a UDP/IP Hardware Stack / UDP Off-load Engine (UOE) with low latency, high-performance targeting 50 GbE net...
122
0.0
UDP/IP Hardware Protocol Stack - 50G
The Digital Blocks DB-UDP-IP-50GbE-AMBA is a UDP/IP Hardware Stack / UDP Off-load Engine (UOE) with low latency, high-performance targeting 50 GbE net...
123
0.0
Secure AHB Performance Subsystem - ARM M3
The Silvaco Secure AHB Performance Subsystem is a high-performance AHB subsystem that allows for a high level of hardware and software security. It in...
124
0.0
Register Indirect RAM Access
The Veriest Register Indirect RAM Access Design IP provides a bridge between the embedded AMBA AHB bus and a configurable number of embedded SRAM devi...
125
0.0
General-Purpose I/O Controller Core
The GPIO core is used to create functions in a system that are not implemented with dedicated controllers, and require simple input and/or output soft...
126
0.0
UFS Device IP
The SmartDV UFS DEVICE IP Core is full-featured, easy-to-use, synthesizable design that is easily integrated into any SoC or FPGA development. The UFS...
127
0.0
RGB to CCIR 601 / 656 Encoder
The Digital Blocks DB1892AXI RGB to CCIR 601 / CCIR 656 Encoder interfaces RGB data along with synchronization signals from a LCD Controller such as D...
128
0.0
AHB AES with DMA
The Advanced Encryption Standard (AES) IP Core is a complete hardware implementation encryption/decryption algorithm described in the U.S. Government ...
129
0.0
AHB Arbiter IP
AHB Arbiter IP core is compliant with AMBA AHB Specification. Through its compatibility, it provides a simple interface to a wide range of low-cost de...
130
0.0
AHB Channel with Decoder and Data Mux
The AHB Channel provides the necessary infrastructure to connect as many as 7 AHB Slaves (numbered 1-7) to an AHB bus Master. The AHB Channel perform...
131
0.0
AHB Decoder IP
AHB Decoder IP core is compliant with AMBA AHB Specification. Through its compatibility, it provides a simple interface to a wide range of low-cost de...
132
0.0
AHB External Bus Interface
The AHB External Bus Interface (EBI) allows a CPU or AHB Master (such as a DMA core) to transmit and receive data to an external device such as an ext...
133
0.0
AHB Lite to SPI Bridge
The AHB-Lite to SPI Bridge is used to translate 32-bit AHB-Lite Writes and Reads to Writes and Reads over a SPI interface. A custom 32-bit protocol i...
134
0.0
AHB Low Power Subsystem - ARM M0
The AHB Low Power Subsystem is an AMBA® based system that is useful as the basic digital infrastructure for building low power SOCs. The subsystem co...
135
0.0
AHB Multilayer Interconnect
The AHB-MLIC is a multi-layer AMBA® AHB bus fabric connecting an arbitrary number of bus masters to an arbitrary number of slaves. The multilayer fa...
136
0.0
AHB Multilayer Interconnect IP
AHB AHB Multilayer Interconnect IP core is compliant with AMBA AHB Specification. Through its compatibility, it provides a simple interface to a wide ...
137
0.0
AHB Performance Subsystem - ARM M0
The AHB Performance Subsystem is an AMBA® based system that is useful as the digital infrastructure for building low power SOCs needing additional per...
138
0.0
AHB Performance Subsystem - ARM M3
The AHB Performance Subsystem is an AMBA® based system that is useful as the digital infrastructure for building low power SOCs needing additional per...
139
0.0
AHB Single Channel DMA Controller
The DMA is a configurable single channel direct memory access controller. The DMA IP Core is a Verilog HDL design that can be used in ASIC, Structured...
140
0.0
AHB Subsystem
The AHB-SBS is an integrated, verified, AMBA® 3.0 interconnect and peripherals subsystem ready for embedded applications using processors with AHB bus...
141
0.0
AHB To APB Bridge IP
AHB2APB Bridge IP core is compliant with AMBA AHB and AMBA APB Specification. Through its compatibility, it provides a simple interface to a wide rang...
142
0.0
AHB to APB Bus Bridge
The AHB to APB Bridge translates an AHB bus transaction (read or write) to an APB bus transaction. This is accomplished via two small state machines ...
143
0.0
AHB Triple DES with DMA
The AHB DES/TDES Encryption/Decryption Engine is a configurable core that interfaces to an AHB microprocessor bus. The Controller encrypts or decrypt...
144
0.0
AHB-Lite to AHB-Lite Asynchronous Bridge
The AHB-Lite to AHB-Lite Asynchronous Bridge translates an AHB-Lite bus transaction (read or write) on one clock domain to an AHB-Lite bus transacti...
145
0.0
AHB/AXI4-Lite to AXI4-Stream Bridge
The MM2ST IP core bridges the streaming interfaces of a peripheral or accelerator to a memory-mapped AMBA® AHB or AXI4-Lite bus. Designed for ease ...
146
0.0
AHB2APB Bridge IP
Truechip's AHB2APB Bridge IP provides chip designers and architects, an efficient way to connect Different Bus Protocol based IPs with reduced latency...
147
0.0
Digital FIR filter with APB interface
The eSi-FIR core provides an interface to filter and decimate time interleaved multi-channel data....
148
0.0
Digital IIR filter with APB interface
A range of 5th to 11th order digital IIR filters for conditioning and optionally decimating data from an external source and to DMA the output into pr...
149
0.0
TileLink To AHB Bridge IP
TileLink to AHB Bridge IP core is compliant with SiFive Tilelink and AMBA AHB Specification. Through its compatibility,it provides a simple interface ...
150
0.0
TileLink To APB Bridge IP
Tilelink2apb Bridge IP core is compliant with SiFive Tilelink and AMBA APB Specification. Through its compatibility, it provides a simple interface to...